RETTOBASE=0, PENDSTSET=0, PENDSVSET=0, ISRPREEMPT=0, PENDSVCLR=0, PENDSTCLR=0, ISRPENDING=0, NMIPENDSET=0
Interrupt Control and State Register
VECTACTIVE | Active exception number |
RETTOBASE | Indicates whether there are preempted active exceptions 0 (0): there are preempted active exceptions to execute 1 (1): there are no active exceptions, or the currently-executing exception is the only active exception |
VECTPENDING | Exception number of the highest priority pending enabled exception |
ISRPENDING | Interrupt pending flag, excluding NMI and Faults 0 (0): No external interrupt pending. 1 (1): External interrupt pending. |
ISRPREEMPT | Indicates whether a pending exception will be serviced on exit from debug halt state 0 (0): Will not service 1 (1): Will service a pending exception |
PENDSTCLR | SysTick exception clear-pending bit 0 (0): no effect 1 (1): removes the pending state from the SysTick exception |
PENDSTSET | SysTick exception set-pending bit 0 (0): write: no effect; read: SysTick exception is not pending 1 (1): write: changes SysTick exception state to pending; read: SysTick exception is pending |
PENDSVCLR | PendSV clear-pending bit 0 (0): no effect 1 (1): removes the pending state from the PendSV exception |
PENDSVSET | PendSV set-pending bit 0 (0): write: no effect; read: PendSV exception is not pending 1 (1): write: changes PendSV exception state to pending; read: PendSV exception is pending |
NMIPENDSET | NMI set-pending bit 0 (0): write: no effect; read: NMI exception is not pending 1 (1): write: changes NMI exception state to pending; read: NMI exception is pending |